Objectives

TERIPHIC will develop transceivers with up to 8 and 16 lanes (i.e. 800 Gb/s and 1.6 Tb/s total capacity), which will be packaged as pluggable and mid-board modules using the QSFP-Double Density (QSFP-DD) and the COBO-16 standard, respectively. After their final assembly, these modules will be mounted on the line cards of MLNX switches, and will be tested both in lab and real DC settings. The path towards these targets is presented through the next seven objectives.

1. Develop EML arrays, PD arrays and polymer motherboards as the key optical components for Terabit transceivers supporting 100 Gb/s transmission per lane in the O-band

2. Develop an automated assembly process for the integration of the optical components and the preparation of the optical subassembly of the Terabit transceivers

3. Fabricate high-speed linear driver arrays and transimpedance amplifier (TIA) arrays on the BiCMOS and InP-DHBT platforms

4. Develop an automated assembly and packaging engine for the preparation of Terabit optical modules leveraging the flexibility of polymer FlexLines

5. Develop small form factor pluggable and mid-board transceivers with 800 Gb/s and 1.6 Tb/s capacity for optical connectivity inside data center environments

6. Evaluate the system performance of the optical modules and demonstrate record 1.6 Tb/s connectivity in real data center environments

7. Prepare the operation of a pilot assembly line and contribute to the definition of standards for Terabit optical modules in datacom technology

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